Because of the highly mobile nature of today's business person, mobile computers are becoming increasingly popular. Mobile computers include, for example, notebook, personal data assistants (PDA's), laptop, and other portable computers. Because the primary function of these electronic devices is to enable the user to execute computationally intensive instructions, such as those required by personal computer software applications, more powerful mobile computers are constantly being developed to keep pace with more demanding software. One highly saleable feature of mobile computers is the length of time the computer can operate between battery charges. Between two mobile computer systems of approximately equal performance, the computer system that is able to operate for a longer period of time between battery charges is considered much more desirable to an end user. Unfortunately, as mobile computing power increases, so increases the drain on the battery. As an example, consider the processor of a typical mobile computer. The processor is commonly considered to be the "brains" of any computer system, and more powerful processors of more powerful computer systems tend to require more electric power to function. Because a processor constitutes one the most significant drains on the battery of a mobile computer, a more powerful computer that includes a more powerful processor tends to drain a battery more quickly than does a less powerful computer, thereby reducing the operational time of the computer system between battery charges.
One method of reducing the amount of electric power drawn by a processor is to design the processor such that it is capable of functioning in two different modes. In a first mode of operation, only the most vital functions of the processor such as, for example, those portions dedicated to monitoring computer system status and user input are functioning. This is referred to as the sleep mode, and it is during this mode that the processor draws very little power from the power supply. In a second mode of operation, the processor is busy executing instructions issued to the processor by the user via a software interface, performing memory management, and other input/output functions. This is referred to as the wake mode, and it is during this mode that the processor consumes a significant amount of power from the power supply.
FIG. 1 is a timing diagram that shows the relationship between signals coupled to processor 10. The signal at the mode signal line coupled to processor 10 switches between a first voltage level, indicating a sleep mode, and a second voltage level indicating a wake mode. When the mode signal switches from the sleep to wake mode (or state), this signifies that the processor is to switch from its sleep to wake mode. The difference in power consumed by processor 10 in these two different modes of operation is indicated by the change in current, I, drawn by processor 10 when switching between the sleep and wake modes.
As shown in FIG. 1, soon after the mode signal signifies that the processor is to switch from a sleep mode to a wake mode, the current drawn by the processor changes from a low current to a high current. Drawing this high current from the power supply indicates that much of the internal circuitry of the processor, which was previously inactive, becomes active, and the processor, along with the entire computer system, is said to have entered its wake mode of operation.
Similarly when the mode signal switches from wake to sleep, this signifies that the processor is to enter into its sleep mode. Once the processor executes the appropriate routines to enable it to shut down portions of its internal circuitry, the power drawn by the processor from the power supply changes from a high current to a low current. At this point the processor, along with the entire computer system, is said to have entered the sleep mode.
By designing a processor to operate in sleep and wake modes, power is conserved because unneeded portions of the processor are shut down when not in use, thereby reducing the overall power consumed by the processor. Unfortunately, there is a side effect associated with switching a processor between sleep and wake modes. The rapid changes in current drawn from a power supply by the processor when the processor switches between modes causes fluctuations in the voltage supplied to the processor by the power supply.
For example, in FIG. 1 it can be seen that while the processor is in sleep mode, the voltage, V, supplied to the processor by the power supply, is at a nominal, constant level during period of time 11. Once the processor switches into the wake mode, however, the current, I, supplied to the processor by the power supply, changes from a low to high value in a relatively short period of time, thereby causing a downwardly spiking voltage supply transient 12. The power supply eventually recovers from the current surge through the processor, and the voltage settles back up to a relatively constant value while the processor is in wake mode during period of time 13.
During the period of time 13, the voltage is typically slightly lower than the nominal voltage level supplied during time 11. This is due to the inability of the power supply to sufficiently drive the high current to processor 10 while the processor is in the wake mode. When the processor then switches back to the sleep mode from the wake mode, causing the current, I, to change from a high to a low value in a relatively short period of time, an upwardly spiking voltage transient 14 occurs. The power supply again recovers from the rapid change in current, lowering the voltage V supplied to processor 10 back to its original nominal level during period of time 15.
The transient range of voltage V is the difference between the peak voltage reached during transient 14 and the minimum voltage reached during transient 12. Typically, processors have specified transient ranges within which the processor is qualified to operate. Outside of this transient range however, a processor is no longer guaranteed to operate properly. As the nominal supply voltage levels for more highly advanced processors decreases, the transient range tolerance of those processors becomes much tighter. Therefore, to provide for reliable operation of advanced computer systems, it becomes necessary to better regulate the voltage supplied by a power supply to a processor such that the transient voltage range is reduced.